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Common problems and solutions of high speed PCB design

With the device operating frequency is higher and higher, the signal integrity of high-speed PCB design problems become a bottleneck of traditional design, the engineer in the design of a complete solution on more and more challenges. Despite the high speed simulation tools and interconnection tools can help designers to solve some problems, but also need more experience in high-speed PCB design to accumulate and in-depth exchanges between the industry.

This is a list of some of the popular concern.

The wiring topology impact on signal integrity

When the signal transmission along the line on the high-speed PCB board may lead to signal integrity issues. Stmicroelectronics of tongyang q: for a set of bus (address, data, command) drive up to 4, and 5 devices (FLASH, SDRAM, etc.), the PCB wiring, is the bus arrive at each device, such as the first to SDRAM, and FLASH... Or bus radial distribution, namely the separation from somewhere, connected to each device respectively. These two approaches on signal integrity, which is better?

Li Baolong  pointed out that the wiring topology impact on signal integrity, mainly reflected in the various nodes signals to reach on time, reflection signals do not match the moment arrived at a same node, so cause the signal quality deterioration. Generally speaking, a star topology structure, can control the same long several branches, make the signal transmission and reflection time delay, achieve a better signal quality. Between the use of topology, want to consider to signal topology node situation, the working principle and the difficulty of wiring.Reflection of different Buffer, to signal the impact is not consistent, so the star topology is not very good solve the data address bus is connected to the FLASH and SDRAM delay, which can not ensure the quality of the signal; High speed signal, on the other hand, generally in the communication between DSP and SDRAM, FLASH when loading rate is not high, so just make sure the actual high speed when high-speed simulation waveform signal effective work node, without having to pay attention to the FLASH waveform; The star topology is Daisy chain topology, such as wiring is difficult, especially a large amount of data address signals using a star topology.

The influence of bonding pad for high speed signal

In PCB, from the design point of view a through hole is mainly composed of two parts: in the middle of the drilling and welding plate around the borehole. Famous for fulonm engineers consult guest solder have any impact on the high-speed signal, to this, bao-long li said: bonding pad has influence to the high speed signal, the impact of similar packaging of components of the device.After detailed analysis, the signal from the IC inside out, after binding wire, pin, encapsulation shell, solder, solder to the transmission lines, all joints in the process will affect the quality of the signal. But the actual analysis, it is difficult to get solder, solder and specific parameters of the pin. So IBIS model is used in the packaging parameters they are summed up, and, of course, such an analysis on the low frequency can receive, but for the higher frequency signal higher precision of simulation is not precise enough. Now it is a trend of using IBIS V - I, V - T describe Buffer characteristics curve, using the SPICE model describes encapsulation parameters.

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